APPLICATIONS OF MODEL-BASED SYSTEMS ENGINEERING METHODS TO VEHICLE AND SUBSYSTEM DESIGN AND OPTIMIZATION Dr. Larry Michaels, Shane Halbach, Neeraj Shidore, Aymeric Rousseau Argonne National Laboratory Sponsored by David

Source URL: www.ndia-mich.org

• Systems engineering
• Military terminology
• Operations research
• Simulation
• Hardware-in-the-loop simulation
• Model-based systems engineering
• Modeling and simulation
• Embedded system
• Predictive engineering analytics
• System-level simulation

Design of Parallel and High Performance Computing HS 2013 Markus P¨ uschel, Torsten Hoefler Department of Computer Science ETH Zurich

Source URL: spcl.inf.ethz.ch

• Parallel computing
• Numerical linear algebra
• Software optimization
• Roofline model
• Software testing
• Matrix multiplication
• Multi-core processor
• FLOPS
• Loop nest optimization
• Matrix multiplication algorithm

Comparison between QuickThread and OpenMP 3.0 under various system load conditions. Copyright © 2009 QuickThread Programming, LLC www.quickthreadprogramming.com

Source URL: www.quickthreadprogramming.com

• Parallel computing
• Fortran
• OpenMP
• Loop optimization
• Standard Performance Evaluation Corporation

OPTIMIZATION AND PERFORMANCE MODELING OF STENCIL COMPUTATIONS ON MODERN MICROPROCESSORS‡ KAUSHIK DATTA†, SHOAIB KAMIL∗†, SAMUEL WILLIAMS∗†, LEONID OLIKER∗, JOHN SHALF∗, KATHERINE YELICK∗† Abstract. St

Source URL: crd.lbl.gov

• Computer architecture
• Cache
• Central processing unit
• Microprocessors
• Computer memory
• CPU cache
• Stencil code
• Loop nest optimization
• Opteron
• POWER5
• Cell
• Multi-core processor

Auto-tuning the 27-point Stencil for Multicore Kaushik Datta2 , Samuel Williams1 , Vasily Volkov2 , Jonathan Carter1 , Leonid Oliker1 , John Shalf1 , and Katherine Yelick1 1 CRD/NERSC, Lawrence Berkeley National Laborat

Source URL: crd.lbl.gov

• Compiler optimizations
• Loop nest optimization
• Stencil code
• Roofline model
• Program optimization
• Stencil
• CPU cache
• Common subexpression elimination
• Scalable locality

Predicting Memory-Access Cost Based on Data-Access Patterns Surendra Byna Xian-He Sun Illinois Institute of Technology {renbyna, sun}@iit.edu Abstract

Source URL: wgropp.cs.illinois.edu

• Cache
• Computer memory
• Computer architecture
• Central processing unit
• Virtual memory
• CPU cache
• Locality of reference
• Loop interchange
• Memory hierarchy
• Loop nest optimization
• Thrashing
• Page table

The Correctness-Security Gap in Compiler Optimization Vijay D’Silva Google Inc. San Francisco, CA Mathias Payer

Source URL: hexhive.github.io

• Software
• Computing
• Compiler optimizations
• Compiler construction
• Programming language implementation
• Undefined behavior
• Optimizing compiler
• Compiler
• Inline expansion
• Constant folding
• Loop-invariant code motion
• Program optimization

Within the newly granted ERC Advanced Grant „From Open to Closed Loop Optimal Control“ postdoc positions will become available in the „Optimization and Optimal Control Group“ led by Prof. Kunisch. The research pl

Source URL: www.ricam.oeaw.ac.at

• Mathematical optimization
• Operations research
• Optimal control

Affine Loop Optimization using Modulo Unrolling in CHAPEL Aroon Sharma, Darren Smith, Joshua Koehler, Rajeev Barua, Michael Ferguson

Source URL: chapel.cray.com

Microsoft PowerPoint - Access-Based Localization for Octagons.pptx

Source URL: nsad2012.ucombinator.org

• Constraint programming
• Logic programming
• Loop quantum gravity
• Data modeling
• Mathematical optimization